Specialization

VLSI Design, Image Processing and Machine Learning

Email

hvohra@thapar.edu

Contact No.: +91-9914923233

Assistant Professor, ECED

email: hvohra@thapar.edu

Biography

Dr. Harpreet Vohra is working with ECED Department, Thapar Institute of Engineering and Technology, Patiala since 2006. She has completed her Ph.D. degree in Test solution development for System on Chip from Thapar Institute of Engineering and Technology in December 2017. Her research interests include VLSI testing, Low power VLSI design, and Machine Learning Techniques.

Education

• Ph.D. in System on-chip test solution development  in Electronics engineering M. Tech VLSI design from CDAC Mohali  (with honors)
• B.Tech. in Electronics and Communication Engineering / P.T.U. Jalandhar / First class

Experience: Total Teaching Experience 14 years

Internship: Six months internship at Zee News Noida.

Teaching Interests:

• Microprocessors and Microcontrollers
• Embedded system
• VLSI testing
• Electronics engineering
• Low power VLSI design

Research Interest:

• System on chip testing
• Low power VLSI Design
• Machine learning application
• Network on chip-based SoC testing
• IOT applications

Publications:

Journals

1. H. Vohra et al, “A low Overhead and Scalable Authentication and Encryption Scheme for Medical Wireless Sensor Networks”, Human-centric Computing and Information Sciences –accepted, 2023

2. A.Yadav, R. Mukherjee, J. K Deewal, G. Singh and H.Vohra, “Advances of 5G Wireless Communication Systems in Healthcare Informatics”, in book: Computational Statistical Methods and Models for Artificial Intelligence, Publisher: Taylor and Francis, October 2022

3. H. Vohra, A. Singh, “Test architecture optimization algorithms for coarse-grain partitioned 3D system-on-chip”, Computers and Electrical Engineering, Vol 101, July 2022;101:108049.

4. H. Vohra and A. Singh “Optimal selective count compatible run-length encoding for SOC test data compression.”, Journal of electronic testing, Vol 32, no. 6, pp: 735-747, 2016

5. H. Vohra and A. Singh “Test data compression using hierarchical block merging technique”,  IET Computers & Digital Technique, Vol 12, No. 4, pp: 176-185, 2018.

6. Vohra, Harpreet, AshimaSingh, and Sukhpal Singh Gill. " An innovative two-stage data compression scheme using adaptive block merging technique.." Integration (2020)..

7. H. Vohra and A. Singh, S.S.Gill, “An innovative two-stage data compression scheme using adaptive block merging technique”, Integration, Vol 73, pp: 68-76, 2020.

8. H. Vohra and A. Singh, “TSV Optimized Test Wrapper Design for Fine Grain Partitioned 3D System on Chip.” International Journal of Innovative Technology and Exploring Engineering, Vol.  9. No.7, 2020.

9.   A. Singh, A. Kaur, and  H.Vohra, “ Identification of Risks and Threats Associated with SPI Programs in SMEs using PCA.”, International Journal of Computer Science and Information Security, Vol. 18, pp: 32-44, 2020.

10. H. Vohra and A. Singh “Survey of System-on-Chip Modular Test Approach”, Journal of VLSI Design Tools & Technology, Vol. 6, No. 4,2016

11. S. Chadha, H. Vohra“Enhanced Compression Code for SOC Test Data Volume Reduction”, International Journal of Computational Engineering & Management, Vol. 18, No. 3, 2015.

12. N. Dewen, H.Vohra, “Test Optimization of 2D SOC using Enhanced ACO Algorithm”, International Journal of Computational Engineering &Management, Vol 18, No. 3.,2015.

13. N. Dewen, P.Agarwal, H. Vohra, “Test Time and Power Optimization of 2D SOCs Using GA and Greedy Algorithm”, Journal of Power Electronics & Power Systems, Vol.18, No. 3, 2015

14. N. Dewen, H.Vohra, “Test Scheduling of Core Based SOC Using Greedy Algorithm”, International Journal of Engineering Research and Applications, Vol. 4, No.9, 2015

15. M.Rani M., H. Vohra, “Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA”, International Journal of Electronics Communication and Computer Technology, Vol. 2 No. 4, 2012

International Conferences

• Sharma, Deepika, Debbrat Ghosh, and Harpreet Vohra. "Test data volume minimization using double hamming distance reordering with mixed RL-Huffman based compression scheme for system-on-chip." 2012 Nirma University International Conference on Engineering (NUiCONE). IEEE, 2012.

Achievement, Awards, and Recognitions

• Awarded university ranker certificate by Honourable chief minister Captain Amrinder Singh, 2004.
• Awarded “Best citizen award” during 73 rd international Human Rights day organized by IEEE Chandigarh sub-section in collaboration with Great Alliance Foundation, India.
• Completed Advanced CAPSL program at TIET, Patiala jointly conducted by Trinity College of Dublin, Ireland and TIET.

Message to Students & Community

Look for something positive in each day, even if some days you have to look a little harder. Be thankful!