Dr. Alpana Agarwal

Professor

Specialization

VLSI Design, Microelectronics

Email

alpana@thapar.edu

Specialization

VLSI Design, Microelectronics

Email

alpana@thapar.edu

  1. Name: Dr. Alpana Agarwal
  2. Designation: Professor
  3. Email/Contact No.: alpana@thapar.edu; 9115608836
  4. Research Area: VLSI Circuits and Systems Design-Synthesis

 

  1. Educational Qualification:(in chronological order starting from highest degree)

Degree

Discipline

Institute/University

Year of Award

Ph D

Electronics Engineering

Thapar University, Patiala

2010

M. Tech.

Solid State Materials

IIT Delhi

1988

M.Sc.

Physics

IIT Delhi

1986

 

  1. Academic experience/Industrial Experience: (in chronological order starting from present employment detail)

Position Held

Name of Organization

Period

Nature of Work

From

To

Professor

Thapar Institute of Engineering & Technology, Patiala

Sept. 4, 2019

Present

Teaching, Research and Administration

Associate Professor

Thapar Institute of Engineering & Technology, Patiala

January 1, 2006

Sept. 3 2019

Teaching, Research and Administration

Assistant Professor

Thapar Institute of Engineering & Technology, Patiala

August 1, 1996

Dec. 31, 2005

Teaching, Research and Administration

Adjunct Faculty

Birla Institute of Technology and Science, Pilani

Jan. 1990

July 1996

Teaching  & Research

Scientist - C

Central Electronics Engineering Research Institute, Pilani

March 25, 19 92

July 30, 1996

Research and Development

Scientist - B

Central Electronics Engineering Research Institute, Pilani

March 25, 1988

March 24, 1992

Research and Development

 

  1. Research Profile:
  • SCI publication: (only numbers) 44
  • Scopus Publications: (only numbers) ~142
  • Others Publications: (only numbers)  10
  • Conference Publications: (only numbers) 17
  • Book/Book Chapters: (only numbers)  8
  • Patents: (only numbers) 4
  • Publication Link: (Google Scholar profile link) Alpana Agarwal - Google Scholar

 

  1. Sponsored Projects

Title

Agency

Budget

Role (PI/ Co-PI)

Duration

SMDP Chips to System Design

MeitY

Rs. 166 Lakhs  

CI (PI)

2015 2021

Low - Complexity Power - Efficient Reconfigurable Implementation of Fractional Order Filters for Weak ECG Nonstationary Biomedical Signal Processing Applications

DST-SERB

Rs. 53.95 Lakhs

Co-PI

2016 – 2019

Special Manpower Development Program for VLSI Design and Related Software (Phase – II)

DietY

Rs. 121 Lakhs

PI

2006 – 2014

Special Manpower Development Program for VLSI Design and Related Software (Phase – I)

DOE

Rs. 75 Lakhs

CI (PI)

1998 – 2005

Worked on several projects at CEERI Pilani

 

  1. Consultancy: NIL

Title

Agency

Budget

Role

Duration

 

 

 

 

 

 

  1. Current membership in professional organizations:
    1. Life Member, Institution of Electronics and Telecommunication Engineers (IETE).
    2. Life Member, Semiconductor Society of India (SSI).
    3. Life Member, Indian Physics Association (IPA).
    4. Life Member, Metrology Society of India (MSI).
    5. Member, VLSI Society of India (VSI).

 

  1. Awards and Honors:
    1. My Ph.D. thesis was chosen as one of the ten best international theses in the domain of VLSI by IEEE /ISVLSI Community and was invited to present my work in ISVLSI 2011.
    2. Best Thesis supervisor in PI category under the aegis of SMDP - VLSI (Phase – II) project. Student Award – Rs 10,000/ - , Supervisor Award – Rs. 15,000/ - and University Award – Rs. 1,50,000/ - (Ministry of Electronics and Information Technology). 2006.
    3. INSA Vising Scientist awarded during 2004 – 05.
    4. Recipient of Cash awards under Performance Incentive Scheme of Thapar Institute of Engineering & Technology almost every year since 2007.
    5. MHRD GATE Fellowship 1986 - 1987.
    6. MD University Merit Award for standing 8th  and College award for standing 1st.
  2. Service activities (within and outside of the institution):
  • Head, Electronics and Communication Engineering Department, Thapar Institute of Engineering & Technology (Jan. 2017 – Dec, 2023).
  • Developed ‘VLSI Design’ Laboratory.
  • Successfully completed ISO/IEC 17025:2017 “ASSESSOR TRAINING PROGRAM” conducted from 29th June to 3rd July 2024 by IQAS.
  • CAPSL Foundation Program: ‘New - Directions’ in Teaching & Learning - Special Purpose Certificate in Academic Practice (SPCert) by Trinity College, Dublin, Ireland.
  • Developed Laboratory manuals for ‘Microprocessors’, ‘Digital Electronics’, ‘Digital VLSI Design’, ‘Analog IC Design’, ‘Hardware Design Languages’.
  • Presiding Officer, Internal Complaints Committee (Jan 2014 – March 2017).
  • Chief Student Counselor, Student Counseling Cell (April 2002 – 2013).
  • UG Incharge 2002 - 04, 2012 - 2014, 2015 – 2016.
  • PG Coordinator (2008 – 2012).
  • Laboratory Incharge, VLSI Design Lab, (2002 – 2015).
  • Laboratory Incharge, VLSI Chips to Systems (2015 – present).
  • Member, DPPC (2014 – Present).
  • Member, DAAC, BOS of ECED (Several occasions, Present).
  • Member, DAAC BE(Mechatronics) (2012 - 2020).
  • Departmental Student Counselor (1997 – 2002).
  • Member of Senate for 1997, 2000, 2004, 2007, 2008 - 09, 2017, 2019 Onwards.
  • President, Environment Society (1997 – 2010).
  • Member UG and PG Curriculum Design Committee.
  • Member UG and PG admission Committees.
  • Member Board of Governors, 2008 - 09.
  • Member Staff Affairs Committee 2008 – 09.
  • Member BOS at various universities.

 

  1. Personalized Profile: (related link required)

 

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