Dr. Bharat Garg
Assistant Professor
Specialization
VLSI Design for Efficient Digital Signal Processing
bharat.garg@thapar.edu
Specialization
VLSI Design for Efficient Digital Signal Processing
- Name: Dr. Bharat Garg
- Designation: Assistant Professor
- Email/Contact No.: bharat.garg@thapar.edu / +91-7974677916
- Research Area: Digital VLSI Design, Hardware Security, VLSI Architectures
- Teaching Interests: Digital System Design, Signals and Systems, FPGA Based System Design, CMOS Circuit Design
- Educational Qualification:
Degree |
Discipline |
Institute/University |
Year of Award |
PhD |
VLSI Design |
ABV-Indian Institute of Information Technology and Management Gwalior |
2017 |
M.Tech |
VLSI Design |
ABV-Indian Institute of Information Technology and Management Gwalior |
2007 |
BE |
Electronics |
RGTU, Bhopal |
2001 |
- Academic experience/Industrial Experience:
Position Held |
Name of Organization |
Period |
Nature of Work |
|
From |
To |
|||
|
Assistant Professor-III |
Thapar Institute of Engineering and Technology, Patiala |
01-07-2021 |
Till Date |
Teaching and Research |
|
Assistant Professor-II |
Thapar Institute of Engineering and Technology, Patiala |
04-09-2019 |
30-06-2021 |
Teaching and Research |
|
Assistant Professor-I |
Thapar Institute of Engineering and Technology, Patiala |
28-03-2018 |
03-09-2019 |
Teaching and Research |
|
Lecturer |
Thapar Institute of Engineering and Technology, Patiala |
28-07-2017 |
27-03-2018 |
Teaching and Research |
|
Assistant Professor |
Shri Ram College of Engg & Management, Banmore |
June 2011 |
June 2012 |
Teaching and Research |
|
Assistant Professor |
Maharana Pratap College of Technology, Gwalior |
Feb 2010 |
July 2011 |
Teaching |
|
ASIC Engineer |
Incube Solution Pvt. Ltd. Hyderabad |
June 2009 |
Jan 2010 |
Design and Development |
|
Elect. Design Engineer |
Cypress Semiconductors, Hyderabad |
Jul 2007 |
March 2009 |
Design and Development |
|
Project Trainee |
Cypress Semiconductors, Hyderabad |
Jan 2007 |
July 2007 |
Design and Development |
|
Sr. Lecturer |
Maharana Pratap College of Technology, Gwalior |
July 2003 |
July 2005 |
Teaching |
|
Lecturer |
Institute of Engineering, Jiwaji University, Gwalior |
Jan 2003 |
April 2003 |
Teaching |
- Research Profile:
- SCI publication: 36
- Scopus Publications: 3
- Others Publications: NIL
- Conference Publications: 19
- Book/Book Chapters: 1
- Patents: 2
- Publication Link: Click Here
- Sponsored Projects
|
Title |
Agency |
Budget |
Role |
Duration |
|
A Lightweight Hardware Logic Locking based Data Encryption Model for Securing IoT Devices from hardware and cyber-attacks |
Data Security Council of India (DSCI) |
6.0 Lacs |
Co-PI |
April 2023 – Dec 2023 |
- Current membership in professional organizations:
- Member IEEE (ID: 94401342)
- Awards and Honors:
- Word’s Top 2% Scientist, Published by Stanford University, 2023
- Word’s Top 2% Scientist, Published by Stanford University, 2022
- PhD Fellowship, MHRD, New Delhi, 2012-17
- M.Tech. Fellowship, MHRD, New Delhi, 2005-07
- Qualified GATE 2017, 2012, 2005, 2004, 2001 (ECE)
- Qualified UEC NET 2013, 2012
- Service activities:
- Warden: Hostel-L, TIET; 24 July 2024 - till date
- Assistant Warden: Hostel-B, TIET; 25 August 2022 – 23 July 2024
- Program Coordinator: M.Tech. (VLSI Design), DECE, TIET; July 2022 - till date
- Vice President, Thapar Movie Club; Aug 2024 – till date
- Lab In-charge: Capstone Project Lab, 2021 – till date
- Personalized Profile:
- LinkedIn: Click Here
- Research Gate: Click Here
- Scopus: Click Here