Specialization

CMOS Analog & Mixed Signal IC Design, Digital IC Design, FPGA, System Design

Email

anils.rawat@thapar.edu

Web Page

• Google Site

Publications and other Research Inputs

SCI/SSCI

1. Ashima Gupta, Anil Singh and Alpana Agarwal,"A Highly-Digital Voltage Scalable 4-bit Flash ADC", IET Circuits, Devices & Systems, Vol. 13, pp. 91 – 97, Jan., 2019.
2. Jupinder Kaur, Prince Prabhakar, Anil Singh and Alpana Agarwal,"A Novel Fast Digital Foreground Gain Error Calibration for Pipelined ADC", accepted for publication in IET Circuits, Devices & Systems, Oct., 2018.
3. Anil Singh, Veena Rawat and Alpana Agarwal, “A Low Power 10-bit 100-MS/s Pipelined ADC in Digital CMOS technology,” published in IET Circuits, Devices & Systems, doi: 10.1049/iet-cds.2016.0525, 2017.
4. Anil Singh, Ayushi Goel and Alpana Agarwal, “A Digital Based Low Power Fully Differential Comparator,” Journal of Circuit, Systems and Computers, Vol. 26, pp. 1750002-14, 2017.
5. Anil Singh and Alpana Agarwal, “Power and Area efficient Pipelined ADC stage in Digital CMOS technology,” IETE-Technical Review, Vol. 34, No.1, pp.66-74 ,2016.
6. Anil Singh and Alpana Agarwal, “Charge pump based MOSFET-only 1.5-bit Pipelined ADC stage in Digital CMOS technology,” International Journal of Electronics, Vol. 103, No.10, pp. 1713-1725, 2016.
7. Anil Singh and Alpana Agarwal, “Digital Background Calibration of Charge pump based Pipelined ADC,” International Journal of Electronics, Vol. 103, No.11, pp. 1941-1953, 2016.

Non-SCI

1. Anil Singh, Sunny Sharma and Alpana Agarwal, “A Fully Differential Gain-Boosted Folded Cascode OPAMP with constant gain in ICMR,” National conference on VLSI Design and Embedded Systems (NCVDES-2011), 12-14th October, 2011, CEERI, Pilani, Rajasthan
2. Anil Singh and Alpana Agarwal, “Modeling Errors in Pipelined ADC using Matlab,” 3rd National Conference on Advances in Metrology (AdMet – 2014), 21-22nd Feb., 2014, Thapar Institute of Engineering & Technology, Patiala

Description of Research Interests

Energy efficient ADCs for future generation devices, low power low jitter PLLs (analog and fully synthesizable), designing of fully synthesizable analog/mixed-signal circuits and artificially intelligent circuits