High Speed & low power VLSI design, Nanotransistor Modeling
- 2006 - 2008 : M.E. - Electronics Engineering with GATE Fellowship, Department of Electronics and Communication Engineering, Punjab Engineering College, Chandigarh, Punjab, India.
- 1998- 2002 : B.E. - Electronics and Communication Engineering with Honors, Department of Electronics and Communication Engineering, Moradabad Institute Of Technology, Moradabad (UP).
- 1995 : Intermediate, Board of High School and Intermed iate Education Uttar Pradesh , Allahabad with 72.8% (Distinction in PCM)
- 1993 : High School, Board of High School and Intermed iate Education Uttar Pradesh, Allahabad with 73.8% (Distinction in Science, Mathematics, Biology and English)
- M.E. - 'Entitled Design, Verification and Implementation on Reconfigurable Hardware of a Fast-Low Power SRAM Address Decoder'.
- M.E. Minor Project - Made a Versatile Digital Thermometer wh ich can be used for industrial as well as domestic purpose
- B.E. Major Project - Entitled 'Electronic Energy Meter with Wireless Data Transmitter and Receiver', Live project at Uttarakhand ( formerly Uttaranchal ) Power Corporation Ltd, Haldwani, Uttarakhand.
- Working as a Lecturer in the Department of Electronics & Communication Engineering, Thapar Institute of Engineering & Technology, Pa tiala, since July-2008,
- Has been worked as a Lecturer in the Depart ment of Electronics & Communication Engineering, IET, MJP Rohilkhand University, Bareilly, UP for two years (2004-2006),
- Has been worked as a Lecturer in the Depart ment of Electronics & Communication Engineering, Govt. Polytechnic, Pilibhit for two years (2002-2004),
- High speed and low power VLSI circuit design,
- MOSFET operation and modeling,
WORKSHOPS & COURSES ATTENDED
- Short term course on 'EMBEDDED SYSTEMS' is completed at NITTTR, Chandigarh,
- Short term course on 'ANTENNA' is completed at NITTTR, Chandigarh,
- Training at 'Prasar Bharti, Broa dcasting Corporation of India, Doordarshan Kendra', Allahabad.
ADMINISTRATIVE & OTHER ACTIVITIES
- Organized 10 days special NSS Camp of 50 students in villages of Bareilly, UP,
P.G. THESES GUIDED
M.E. Theses Guided
- Analysis and design of a DRAM cell for low leakage,
- Analysis and design of a SRAM cell for low leakage power,
- Analysis, design and hardware implementation of a Vedic multiplier with BIST capability