Dr. Alpana Agarwal

Professor and Head

Specialization

VLSI Design, Microelectronics

Email

alpana@thapar.edu

Specialization

VLSI Design, Microelectronics

Email

alpana@thapar.edu

 

Contact No.: 9115608836, 9417397370

 

Education:

  • Ph.D. Topic –“Synthesis of Analog IC Building Blocks” under the supervision of Dr. Chandra Shekhar, CEERI Pilani.
  • M.Tech. (Solid-State Materials), GATE Scholarship recipient, Indian Institute of Technology, New Delhi.
  • M.Sc. (Physics), Indian Institute of Technology, New Delhi.

 

Experience

Academic (~30years)

  • Professor at Thapar Institute of Engineering & Technology, Patiala from September 4, 2019, to present.
  • Associate Professor at Thapar Institute of Engineering & Technology, Patiala from January 1, 2006, to August 2019.
  • Assistant Professor at Thapar Institute of Engineering & Technology, Patiala from August 1, 1996, to December 31, 2005.
  • Birla Institute of Technology and Science, Pilani, Adjunct Faculty, 1990 – 1996.

Research (~32 years)

  • Central Electronics Engineering Research Institute, Pilani, Scientist - B, March 25, 1988 – March 24, 1992.
  • Central Electronics Engineering Research Institute, Pilani, Scientist - C, March 25, 19 92 – July 30, 1996.
  • Thapar Institute of Engineering & Technology, Patiala since August 1, 1996.

 

Sponsored Research Projects:

  • Completed/Ongoing 10 projects worth more than four (4) Crores from DoE/DIT/ DeitY, DST.
  • Worked on several projects at CEERI Pilani.
  • SMDP Chips to System Design, MeitY sponsored, Rs. 166 Lakhs, (Consortium Budget 99.97 Crores) 2015 - 2020, (Chief Investigator)  Ongoing.
  • Low - Complexity Power - Efficient Reconfigurable Implementation of Fractional Order Filters for Weak ECG Nonstationary Biomedical Signal Processing Applications, DST-SERB Sponsored, Rs. 53.95 Lakhs, 2016 – 19. (Co-PI ) Ongoing.
  • Special Manpower Development Program for VLSI Design and Related Software (Phase – II), DietY sponsored, Rs. 121 Lakhs, 1998 – 2005. (Coordinator).
  • Special Manpower Development Program for VLSI Design and Related Software (Phase – I), DOE-sponsored, Rs. 75 Lakhs, 1998 – 2005. (Coordinator).

 

Major Publications:

  • Ashima Gupta, Anil Singh and Alpana Agarwal, “Highly-Digital Voltage Scalable 4-bit Flash ADC”, IET Circuits, Devices & Systems, Vol.13, pp. 91-97, 2019.
  • Ashima Gupta, Anil Singh and Alpana Agarwal, “Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC,” Journal of Circuits, Systems and Computers, p. 2050073, 2019.
  • Jagdeep Kaur Sahani, Anil Singh and Alpana Agarwal, “A 2.3 mW Multi-frequency Clock Generator with -137 dBc/Hz Phase Noise VCO in 180nm Digital CMOS Technology” accepted in Journal of circuit, systems and computers, Sept. 2019.
  • Jagdeep Kaur Sahani, Anil Singh and Alpana Agarwal, “A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology,” accepted in Journal of circuit, systems and computers, Sept. 2019.
  • Jupinder Kaur, Prince Prabhakar, Anil Singh and Alpana Agarwal, "Fast digital foreground gain error calibration for pipelined ADC," in IET Circuits, Devices & Systems, vol. 13, no. 2, pp. 219-225, 3 2019.
  • Anil Singh and Alpana Agarwal, "Charge pump - based MOSFET - only 1.5 - bit pipelined ADC stage in digital CMOS technology", International Journal of Electronics, Vo. 103, No.10, pp. 1713 - 1725, 2016 (IF 0.729).
  • Anil Singh and Alpana Agarwal, "Digital background calibration of charge pump based pipelined ADC", International Journal of Electronics, Vol. 103, No.11, pp. 1941 - 1953, 2016 (IF 0.729).
  • Anil Singh and Alpana Agarwal, "Power and Area Efficient Pipelined ADC Stage in Digital CMOS Technology", IETE Technical Review, Vol. 34, No.1, pp. 66 - 74, 2016 (IF 1.330).
  • Anil Singh, Ayushi Goel, and Alpana Agarwal, "A Digital - Based Low - Power Fully Differential Comparator", Journal of Circuits, Systems, and Computers, Vol. 26, pp. 1750002 - 14, 2017, (IF 0.47).
  • Anil Singh, Veena Rawat and Alpana Agarwal, "A Low Power 10 - bit 100 - MS/s Pipelined ADC in Digital CMOS technology", accepted for publication in IET Circuits, Devices & System, 2017 (1.092).

 

International Conferences

  • Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal, “A High Resolution and Low Jitter 5-bit Flash TDC Architecture for High-Speed Intelligent Systems”, In Proceedings of International Conference, Intelligent Systems (IntelliSys); London, UK. (Sep. 2019). pp. 266-278.
  • Ajay Kumar and Alpana Agarwal, Research Issues Related to Cryptography Algorithms and Key Generation for Smart Grid: A Survey, 7th International IEEE India International Conference on Power Electronics (IICPE – 2016), November 17 – 19, 2016.
  • Mansi Sharma and Alpana Agarwal, Survey on Authentication and Encryption Techniques for Smart Grid Communication, 7th International IEEE India International Conference on Power Electronics (IICPE – 2016), November 17 – 19, 2016.
  • Manu Bansal and Alpana Agarwal, Genetic Algorithm for Ordering and Reduction of B DDs for MIMO Circuits, The Third International Conference on Innovative Computing Technology London, UK, August 29 - 31, 2013
  • Madhusoodan Agarwal &Alpana Agarwal, A Combined CMOS Reference Circuit with Supply and Temperature Compensation, 17th International Symposium on VLSI Design and Test (VDAT2013), July 28 – 30, 2013.
  • Alpana Agarwal and Chandra Shekhar, Synthesis of Analog IC Building Blocks, IEEE Annual Symposium on VLSI (ISVLSI), Chennai, India July 4 - 6, 2011.
  • Alpana Agarwal,  A Voltage controlled CMOS VGA with 40 dB Dynamic range for MEMS Applications, Symposium H: MEMS Technology and Devices in International Conference on Materials for Advanced Technologies 2007, July 1 - 6, 2007, Singapore.
  • Varun Jindal and Alpana Agarwal, Carry Circuitry for LUT - Based FPGA, Proceedings of the 17th International Conference on VLSI Design 2004 and ICES - 3, Jan. 7 - 9, 2004, Mumbai.

 

Other Publications

  • 35 in Peer-reviewed International and national journals and conferences.
  • Reviewer in IEEE, Elsevier, Francis and Taylor, Springer journals.

 

Patent Filed

  • Anil Singh and Alpana Agarwal, "Fully differential clocked comparator for pipelined analog-to-digital converter", filed Indian patent with Acknowledgement no. TEMP/E - 1/8400/2016 - DEL, Mar. 2016.

 

Thesis Guided

  • Guided ~80 ME/M.Tech thesis.
  • Guided 2 Ph.D. students.
  • Ongoing 8 Ph.D. student guidance.

 

Foreign Visits

  • Deputed to Trinity College, Dublin from Oct. 5 – Nov. 1, 2015, for learning international academic practices.
  • Visited Singapore and Australia for conference presentations.

 

Expert Talks

  • Delivered more than 25 Expert/Invited talks at IIT Delhi, NIT Kurukshetra, MNIT Jaipur, NIT Jalandhar, NIT Hamirpur, PEC Chandigarh, USIC and Electronics Department – Kurukshetra University, BITS Pilani, CEERI Pilani, Chitkara University, MITS Lakshmangarh, MM University.
  • Delivered Invited Talks at about 15 conferences and workshops.

 

Short Term Courses/Workshops/Conferences Organized: 15

 

Short Term Courses/Workshops/Conferences Attended: More than 50

 

Course Material Developed

  • VLSI Design Concepts, AICTE, 2002
  • Digital Electronic Circuits, DDE, Thapar Institute of Engineering & Technology, 2006.
  • Electronic Devices and Circuits, DDE, Thapar Institute of Engineering & Technology, 2006.

 

Honours and Awards

  • My Ph.D. thesis was chosen as one of the ten best international thesis in the domain of VLSI by IEEE /ISVLSI Community and was invited to present my work in ISVLSI 2011.
  • Best Thesis supervisor in PI category under the aegis of SMDP - VLSI (Phase – II) project. Student Award – Rs 1 0,000/ - , Supervisor Award – Rs. 15,000/ - and University Award – Rs. 1,50,000/ - (Ministry of Electronics and Information Technology). 2006.
  • INSA Vising Scientist awarded during 2004 – 05.
  • Recipient of Cash awards under Performance Incentive Scheme of Thapar Institute of Engineering & Technology almost every year since 2007.
  • MHRD GATE Fellowship 1986 - 1987.
  • MD University Merit Award for standing 8th  and College award for standing 1st.

 

Membership of Professional Organizations

  • Life Member, Institution of Electronics and Telecommunication Engineers (IETE).
  • Life Member, Semiconductor Society of India (SSI).
  • Life Member, Indian Physics Association (IPA).
  • Life Member, Metrology Society of India (MSI).
  • Member, VLSI Society of India (VSI).

 

Major Administrative Responsibilities

  • Head, Electronics and Communication Engineering Department, Thapar Institute of Engineering & Technology (Jan. 2017 onwards).
  • Presiding Officer, Internal Complaints Committee ( Jan 2014 – March 2017 ).
  • UG Incharge 2002 - 04, 2012 - 2014, (2015 – 2016 ).
  • PG Coordinator (2008 – 2012).
  • Laboratory Incharge, VLSI Design Lab, (2002 – 2015).
  • Laboratory Incharge, VLSI Chips to Systems (2015 – present).
  • Member, DPPC (2014 – Present).
  • Member, DAAC, BOS of ECED (Several occasions, Present).
  • Member, DAAC BE(Mechatronics) (2012 - Present).
  • Chief Student Counselor, Student Counseling Cell (April 2002 – 2013).
  • Departmental Student Counselor (1997 – 2002).
  • Member of Senate for 1997, 2000, 2004, 2007, 2008 - 09, 2017.
  • President, Environment Society (1997 – 2010).

 

Other Academic / Co-curricular / extracurricular activities

  • CAPSL Foundation Program: ‘New - Directions’ in Teaching & Learning - Special Purpose Certificate in Academic Practice (SPCert) by Trinity College, Dublin, Ireland.
  • Developed ‘VLSI Design’ Laboratory.
  • Developed Laboratory manuals for ‘Microprocessors’, Digital Electronics’, ‘Digital VLSI Design’, ‘Analog IC Design’, Hardware Deion Languages’.
  • Member UG and PG Curriculum Design Committee.
  • Member UG and PG admission Committee.
  • Member Board of Governors, 2008 - 09.
  • Member Staff Affairs Committee 2008 – 09.
  • Member BOS at various universities.
  • Examined Ph.D., ME/MTech. Thesis evaluations at various universities.