Dr. Sujit Kumar Patel

Assistant Professor

Specialization

VLSI Signal Processing

Email

sujit.patel@thapar.edu

Specialization

VLSI Signal Processing

Email

sujit.patel@thapar.edu

Subjects

Electrical Circuit Analysis, Electronic Devices and Circuits, Analog Electronics, Semiconductor Devices, Digital Electronics, Signals and Systems, VLSI Circuits & Systems Design, Analog VLSI Design, FPGA Based System Design.

Membership of Professional Institutions, Associations, Societies

  • IEEE Member

Publications and other Research Outputs

Journal Publications:

  1. S.K. Patel and S. K. Singhal, “Area-Delay and Energy Efficient Multi-operand Binary Tree Adder,” IET Circuits, Devices and Systems, 2020. (Available online DOI: 10.1049/iet-cds.2019.0443). (SCI)
  2. B. Garg and S.K. Patel, “LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing,” Journal of Electronic Testing, 36, pp. 429–437, 2020.  (Available online: https://doi.org/10.1007/s10836-020-05883-4). (SCI)
  3. B. Garg and S.K. Patel, “Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency,” Springer Journal of Signal Processing Systems, 2020. (Available online: https://doi.org/10.1007/s11265-020-01542-1. (SCI)
  4. S K. Rai, R. Pandey, B. Garg and S.K. Patel, “A novel design of current differencing transconductance amplifier with high transconductance gain and enhanced bandwidth,” Turkish Journal of Electrical Engineering & Computer Sciences, 2020. (Available online DOI: 10.3906/elk-1909-12). (SCI)
  5. S.K. Patel, B. Garg and S. K. Rai, “An efficient accuracy reconfigurable CLA adder designs using complementary logic,” Journal of Electronic Testing, vol. 36, pp. 135–142, 2020.  (https://doi.org/10.1007/s10836-019-05851-7). (SCI)
  6. S.K. Patel, B. Garg and S K. Rai, “A power and area efficient approximate carry skip adder for error resilient applications,” Turkish Journal of Electrical Engineering & Computer Sciences, vol. 28, pp-443-457, Jan 2020. (https://doi.org/10.3906/elk-1907-72). (SCI)
  7. S.K. Singhal, B.K. Mohanty, S.K. Patel and G. Saxena, “Efficient diminished-1 modulo 2n +1  adder using parallel prefix adder,” Journal of Circuits, Systems and Computers, 2019. (Available online: https://doi.org/10.1142/S0218126620501868). (SCI)
  8. B. K. Mohanty, P. K. Meher and S. K. Patel, “LUT optimization for distributed arithmetic based block least mean square adaptive filter,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1926-1935, May 2016. (SCI)
  9. P. K. Meher, B. K. Mohanty, S. K. Patel, S. Ganguly and T. Srikanthan, “Efficient VLSI architecture for decimation-in-time fast Fourier transform of real-valued data”, IEEE Transaction on Circuits and Systems-I, Regular Papers, vol.62, no.12, pp.2836-2845, Dec. 2015. (SCI)
  10. B. K. Mohanty, S. K. Patel, “Efficient very large-scale integration architecture for variable length block least mean square adaptive filter,” IET Journal on Signal Processing, vol. 9, no. 8, pp. 605-610, Oct. 2015. (SCI)
  11. B. K. Mohanty, S. K. Patel, “Area-delay-power efficient carry select adder,” IEEE Transaction on Circuits and Systems-II, Express Brief, vol. 61, no. 6, pp. 418-422, June 2014. (SCI)

 

 

Conference Publications:

  1. S.K. Patel, B. Garg, S.K. Rai and A. Mahajan, “Area-delay efficient and low-power carry skip adder for high performance computing systems,” Proc. in 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Organized at NIT Rourkela, Odissa, India, pp.-295-298, 20019. 

Description of Research Interests

Design of high performance VLSI systems for the signal processing algorithms, Low-power arithmetic components design.