Dr. Sujit Kumar Patel

Assistant Professor

Specialization

VLSI Signal Processing

Email

sujit.patel@thapar.edu

Specialization

VLSI Signal Processing

Email

sujit.patel@thapar.edu

 

Biography:

Dr. Sujit K. Patel received the B.E. degree in Electronics and Communication Engineering from Jabalpur Engineering College, Jabalpur, India, and M.Tech. degree from the DA-IICT, Gandhinagar, Gujarat, India, in 2006 and 2009, respectively. He has completed his Ph. D. from Jaypee University of Engineering and Technology, Guna, (M.P.) in 2016. He has 13 years of teaching experience and currently he is an Assistant Professor with ECE department since July 2017, Thapar Institute of Engineering and Technology, Patiala, Punjab, India. His research interest includes the design of VLSI systems for the signal and image processing algorithms, low-power circuits for arithmetic components. He has published 14 SCI papers which includes 3 IEEE transactions and 3 IET journals.

Subjects

Electrical Circuit Analysis, Electronic Devices and Circuits, Analog Electronics, Semiconductor Devices, Digital Electronics, Signals and Systems, VLSI Circuits & Systems Design, Analog VLSI Design, FPGA Based System Design.

Research Interest:

Design of high-performance VLSI systems for signal and image processing algorithms, low-power circuit for arithmetic components (adders and multipliers).

Membership of Professional Institutions, Associations, Societies

  • IEEE Member

Publications and other Research Outputs

Journal Publications:

  1. K. Anjali Rao,  A. Kumar, Dmitrii Kaplun, S. K. Patel, Neetesh Purohit, “Design of low complexity parallel poly-phase finite impulse response filter using coefficient symmetry,” IET Circuits, Devices and Systems, Vol. 17, Iss. 1, pp. 29-37, 2023. (DOI: https://doi.org/10.1049/cds2.12134). (SCI) 

  2. S.K. Singhal, S.K. Patel, A. Mahajan and G. Saxena, "Area-Delay Efficient Radix-4 8x8 Booth Multiplier for DSP Applications," Turkish Journal of Electrical Engineering & Computer Sciences, Vol 29, page 29: 2012 – 2028, 2021. (SCI)

  3. B. Garg and S.K. Patel, “Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications,” Wireless Personal Communications, Vol 118, pages 919–931, 2021. ( https://doi.org/10.1007/s11277-020-08051-1). (SCI)

  4. S.K. Patel and S. K. Singhal, “Area-Delay and Energy Efficient Multi-operand Binary Tree Adder,” IET Circuits, Devices and Systems, Vol. 14, Iss. 5, pp. 586-593, 2020. (DOI: 10.1049/iet-cds.2019.0443). (SCI)

  5. B. Garg and S.K. Patel, “LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing,” Journal of Electronic Testing, 36, pp. 429–437, 2020.  (Available online: https://doi.org/10.1007/s10836-020-05883-4). (SCI)

  6. B. Garg and S.K. Patel, “Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency,” Springer Journal of Signal Processing Systems, Vol 93, pp. 99–111, 2021. (SCI)

  7. S K. Rai, R. Pandey, B.  Garg and S.K. Patel, “A novel design of current differencing transconductance amplifier with high transconductance gain and enhanced bandwidth,” Turkish Journal of Electrical Engineering & Computer Sciences, 2020. (Available online DOI: 10.3906/elk-1909-12). (SCI)

  8. S.K. Patel, B. Garg and S. K. Rai, “An efficient accuracy reconfigurable CLA adder designs using complementary logic,” Journal of Electronic Testing, vol. 36, pp. 135–142, 2020.  (https://doi.org/10.1007/s10836-019-05851-7). (SCI)

  9. S.K. Patel, B. Garg and S K. Rai, “A power and area efficient approximate carry skip adder for error resilient applications,” Turkish Journal of Electrical Engineering & Computer Sciences, vol. 28, pp-443-457, Jan 2020. (https://doi.org/10.3906/elk-1907-72). (SCI)

  10. S.K. Singhal, B.K. Mohanty, S.K. Patel and G. Saxena, “Efficient diminished-1 modulo 2n +1  adder using parallel prefix adder,” Journal of Circuits, Systems and Computers, 2019. (Available online: https://doi.org/10.1142/S0218126620501868). (SCI)

  11. B. K. Mohanty, P. K. Meher and S. K. Patel, “LUT optimization for distributed arithmetic based block least mean square adaptive filter,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1926-1935, May 2016. (SCI)

  12. P. K. Meher, B. K. Mohanty, S. K. Patel, S. Ganguly and T. Srikanthan, “Efficient VLSI architecture for decimation-in-time fast Fourier transform of real-valued data”, IEEE Transaction on Circuits and Systems-I, Regular Papers, vol.62, no.12, pp.2836-2845, Dec. 2015. (SCI)

  13. B. K. Mohanty, S. K. Patel, “Efficient very large-scale integration architecture for variable length block least mean square adaptive filter,” IET Journal on Signal Processing, vol. 9, no. 8, pp. 605-610, Oct. 2015. (SCI)

  14. B. K. Mohanty, S. K. Patel, “Area-delay-power efficient carry select adder,” IEEE Transaction on Circuits and Systems-II, Express Brief, vol. 61, no. 6, pp. 418-422, June 2014. (SCI)

Conference Publications:

  1. P. Sharma and S. K. Patel, "An Automation Methodology for Amelioration of SpyGlassCDC Abstract View Generation Process," IEEE 6th International Conference for Convergence in Technology 2021, Lonavala, Pune, India.

  2. S.K. Patel, B. Garg, S.K.  Rai and A. Mahajan, “Area-delay efficient and low-power carry skip adder for high performance computing systems,” Proc. in 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Organized at NIT Rourkela, Odissa, India, pp.-295-298, 2019.   

Description of Research Interests

Design of high performance VLSI systems for the signal processing algorithms, Low-power arithmetic components design.

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